Semiconductor constructions may comprise integrated circuitry supported by a semiconductor wafer (such as, for example, a monocrystalline silicon wafer). The integrated circuitry may include logic and/or one or more memory arrays (such as, for example, dynamic random access memory (DRAM), and/or NAND memory).
The semiconductor constructions may also comprise electrically conductive layers utilized to connect components of the integrated circuitry with bond pad regions. Such electrically conductive layers may be referred to as redistribution layers, in that they redistribute electrical connections from one portion of a semiconductor construction to another. Alternatively, such electrically conductive layers may be referred to as bond pad supporting layers.
The bond pad regions may comprise one or more electrically conductive layers formed over the bond pad supporting layers, and may be suitable for connection to wire bonds, solder, or other materials utilized for electrical connection to circuitry external of the semiconductor construction.
Difficulties may be encountered during formation of the bond pad regions. Specifically, the bond pad regions may be plated onto the bond pad supporting layers by dipping the semiconductor construction within a plating bath. The semiconductor construction will have a front side comprising the bond pad supporting layers, and will have a back side in opposing relation to the front side. If plating occurs on the back side, such can waste plating components, and such may also form electrically conductive structures which compromise performance of the integrated circuitry associated with the wafer.
One method of addressing such difficulties is to form an electrically insulative layer across the back side prior to dipping the semiconductor construction within a plating bath. However, formation of the electrically insulative layer comprises flipping the semiconductor construction so that the back side surface is up, followed by chemical vapor deposition (CVD) of insulative material on the back side surface. The semiconductor construction is then flipped back over so that the front side surface is up for subsequent processing. The flipping of the semiconductor construction can cause abrasions or other defects. It is desired to develop methods which avoid plating on the back side surface of a semiconductor construction, and yet which also avoid the problematic flipping of the semiconductor construction.
Another aspect of the prior art is that there will often be one or more passivation layers formed over the bond pad supporting layers. Such passivation layers may include a silicon nitride-containing layer. It is often desired to anneal the silicon nitride-containing passivation layer at a temperature sufficiently high to promote hydrogen migration from the passivation layer, and/or otherwise thermally treat the passivation layer. Such temperature may be at least about 400° C.
The anneal adds an additional process step. As each additional process step reduces throughput, creates risk of error, and increases cost; it is desired to reduce the number of process steps.